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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4641d 07h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4641d 08h /
354 Whitespace cleanup olof 4641d 08h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4643d 10h /
352 Removed delayed assignments from rtl code olof 4647d 16h /
351 Turn defines into parameters in eth_cop olof 4656d 05h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4656d 06h /
349 Make all parameters configurable from top level olof 4657d 07h /
348 Added option to dump VCD files olof 4658d 06h /
347 Added information about running with Icarus Verilog olof 4658d 06h /
346 Updated project location olof 4658d 08h /
345 Temporarily disable failing tests olof 4658d 10h /
344 bit 9 in phy control register is self clearing olof 4664d 12h /
343 Address miss should not be asserted on short frames olof 4668d 08h /
342 Added cast to avoid inequality when comparing different data types olof 4668d 08h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4668d 08h /
340 Don't fail if log dir already exists olof 4669d 06h /
339 Added basic support for Icarus Verilog olof 4670d 05h /
338 root 5462d 11h /
337 root 5518d 13h /
336 Added old uploaded documents to new repository. root 5519d 16h /
335 New directory structure. root 5519d 16h /
334 Minor fixes for Icarus simulator. igorm 6967d 18h /
333 Some small fixes + some troubles fixed. igorm 6968d 06h /
332 Case statement improved for synthesys. igorm 6981d 11h /
331 Tests for delayed CRC and defer indication added. igorm 6996d 13h /
330 Warning fixes. igorm 6996d 13h /
329 Defer indication fixed. igorm 6996d 14h /
328 Delayed CRC fixed. igorm 6996d 15h /
327 Defer indication fixed. igorm 6996d 15h /

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