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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4253d 18h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4253d 18h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4253d 20h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4253d 21h /
354 Whitespace cleanup olof 4253d 21h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4255d 23h /
352 Removed delayed assignments from rtl code olof 4260d 04h /
351 Turn defines into parameters in eth_cop olof 4268d 18h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4268d 19h /
349 Make all parameters configurable from top level olof 4269d 20h /
348 Added option to dump VCD files olof 4270d 19h /
347 Added information about running with Icarus Verilog olof 4270d 19h /
346 Updated project location olof 4270d 21h /
345 Temporarily disable failing tests olof 4270d 23h /
344 bit 9 in phy control register is self clearing olof 4277d 01h /
343 Address miss should not be asserted on short frames olof 4280d 21h /
342 Added cast to avoid inequality when comparing different data types olof 4280d 21h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4280d 21h /
340 Don't fail if log dir already exists olof 4281d 19h /
339 Added basic support for Icarus Verilog olof 4282d 18h /

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