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Rev Log message Author Age Path
359 Verilator linting fixes olof 4076d 03h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4077d 17h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4077d 17h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4077d 19h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4077d 20h /
354 Whitespace cleanup olof 4077d 20h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4079d 22h /
352 Removed delayed assignments from rtl code olof 4084d 04h /
351 Turn defines into parameters in eth_cop olof 4092d 18h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4092d 18h /
349 Make all parameters configurable from top level olof 4093d 19h /
348 Added option to dump VCD files olof 4094d 18h /
347 Added information about running with Icarus Verilog olof 4094d 18h /
346 Updated project location olof 4094d 20h /
345 Temporarily disable failing tests olof 4094d 22h /
344 bit 9 in phy control register is self clearing olof 4101d 00h /
343 Address miss should not be asserted on short frames olof 4104d 20h /
342 Added cast to avoid inequality when comparing different data types olof 4104d 20h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4104d 20h /
340 Don't fail if log dir already exists olof 4105d 18h /

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