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Rev Log message Author Age Path
359 Verilator linting fixes olof 4618d 11h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4620d 01h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4620d 02h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4620d 03h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4620d 04h /
354 Whitespace cleanup olof 4620d 05h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4622d 06h /
352 Removed delayed assignments from rtl code olof 4626d 12h /
351 Turn defines into parameters in eth_cop olof 4635d 02h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4635d 02h /
349 Make all parameters configurable from top level olof 4636d 03h /
348 Added option to dump VCD files olof 4637d 02h /
347 Added information about running with Icarus Verilog olof 4637d 03h /
346 Updated project location olof 4637d 05h /
345 Temporarily disable failing tests olof 4637d 06h /
344 bit 9 in phy control register is self clearing olof 4643d 08h /
343 Address miss should not be asserted on short frames olof 4647d 04h /
342 Added cast to avoid inequality when comparing different data types olof 4647d 05h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4647d 05h /
340 Don't fail if log dir already exists olof 4648d 02h /
339 Added basic support for Icarus Verilog olof 4649d 02h /
338 root 5441d 07h /
337 root 5497d 09h /
336 Added old uploaded documents to new repository. root 5498d 12h /
335 New directory structure. root 5498d 12h /
334 Minor fixes for Icarus simulator. igorm 6946d 15h /
333 Some small fixes + some troubles fixed. igorm 6947d 02h /
332 Case statement improved for synthesys. igorm 6960d 08h /
331 Tests for delayed CRC and defer indication added. igorm 6975d 09h /
330 Warning fixes. igorm 6975d 10h /

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