OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 49

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 HASH0 and HASH1 register read/write added. mohor 8079d 18h /
48 RxOverRun added to statuses. mohor 8079d 21h /
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 8079d 21h /
46 HASH0 and HASH1 registers added. mohor 8079d 21h /
45 Ethernet Datasheet added. mohor 8080d 03h /
44 Ethernet Datasheet added to cvs. mohor 8080d 03h /
43 Tx status is written back to the BD. mohor 8081d 05h /
42 Rx status is written back to the BD. mohor 8083d 22h /
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8086d 00h /
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 8086d 21h /
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8091d 01h /
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8100d 03h /
37 Link in the header changed. mohor 8100d 04h /
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8146d 02h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8148d 23h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8148d 23h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8149d 03h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8149d 04h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8149d 04h /
30 BD section updated. mohor 8151d 01h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8171d 00h /
28 New release. Name changed to lower case. mohor 8173d 15h /
27 File names changed to lower case. mohor 8173d 15h /
26 First release of product brief. mohor 8173d 15h /
25 First release of product brief. mohor 8173d 16h /
24 Log file added. mohor 8196d 03h /
23 Number of addresses (wb_adr_i) minimized. mohor 8196d 03h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8196d 05h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8197d 02h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8220d 23h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.