OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 84

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
84 LinkFail signal was not latching appropriate bit. mohor 8083d 13h /
83 MAC address recognition was not correct (bytes swaped). mohor 8083d 13h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8083d 15h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8083d 15h /
80 Small fixes for external/internal DMA missmatches. mohor 8087d 17h /
79 RetryCntLatched was unused and removed from design mohor 8087d 18h /
78 WB_SEL_I was unused and removed from design mohor 8087d 18h /
77 Interrupts changed mohor 8087d 18h /
76 Interrupts changed in the top file mohor 8087d 18h /
75 r_Bro is used for accepting/denying frames mohor 8087d 18h /
74 Reset values are passed to registers through parameters mohor 8087d 18h /
73 Number of interrupts changed mohor 8087d 18h /
72 Retry is not activated when a Tx Underrun occured mohor 8091d 21h /
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 8095d 23h /
70 Small fixes. mohor 8096d 00h /
69 Define missmatch fixed. mohor 8096d 21h /
68 Registered trimmed. Unused registers removed. mohor 8097d 20h /
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8097d 21h /
66 Testbench fixed, code simplified, unused signals removed. mohor 8098d 03h /
65 Testbench fixed, code simplified, unused signals removed. mohor 8098d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.