| Rev |
Log message |
Author |
Age |
Path |
| 44 |
Changed design for Kintex 7 based boards (AFCK, KC705) so that
they use the VEXTPROJ environment for VCS friendly project management
(described in http://doi.org/10.1117/12.2247944 ) |
wzab |
3214d 14h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 43 |
Removed latch on "dbg" signal |
wzab |
3214d 14h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 42 |
KC705 design upgraded to Vivado 2016.4
Corrrected indentation in a few files in AFCK design |
wzab |
3214d 18h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 41 |
The AFCK project upgraded to Vivado 2016.4 |
wzab |
3214d 19h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 40 |
The "jumbo frame version" renamed from "experimental" to "stable". |
wzab |
3215d 00h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 37 |
Added new design for AFCK board, which uses 8 10 Gbps links.
Additionally added I2C control of the AFCK Si57x based clock.
The I2C controller is driven via VIO blocks controlled by JTAG
interface from Vivado Tcl console.
Tcl scripts are in the fpga/src/AFCK/i2c_tools directory.
To configure clock to 156.25MHz, and to route it to links,
change directory to fpga/src/AFCK/i2c_tools and do
"source start_10g_links.tcl".
After the clock is reprogrammed, reconfigure the FPGA again
(it seems, that there is a problem with reseting links after
clock is reconfigured). |
wzab |
3816d 13h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 36 |
Added signals needed to ensure, that Si570/1 chip generates the clock.
Added signals driving the rate select lines in the SFP+ modules high.
Added two XDC files - the first one for FM-S14 in the FMC1
connector, the second one for FM-S14 in the FMC2 connector. |
wzab |
3832d 16h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 35 |
Changed comment in definition of the descriptor record
Updated IP cores in project for KC705 (to Vivado 2014.4) |
wzab |
3935d 15h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 33 |
Added script for automatic compilation of FADE for AFCK, using Vivado 2014.4 |
wzab |
3952d 01h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 32 |
Added the 4-channel FADE test implementation for the AFCK board. |
wzab |
3952d 05h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 27 |
Added file fade_one_channel, allowing to implement multiple FADE instances in a single FPGA. |
wzab |
3980d 03h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 26 |
Corrected small bug in CRC update in eth_sender8,vhd
Added counter of retransmitted packets.
Some minor changes in delay update parameters. |
wzab |
4014d 14h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 23 |
Added script allowing for batch compilation of FADE 10G for Atlys.
Just run build_proj_atlys.sh
Removed compilation of receiver2.c (which has been deleted) in the Makefile.
Slightly changed order of operation in the receiver2t.c |
wzab |
4038d 17h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
| 22 |
Sources reorganized so, that each ".xci" is in a separate directory.
Added script for rebuilding of Vivado project for KC705.
Just run the build_proj_kc705 script, and the project
will be created as kc705_10g3.xpr in the kc705_10g3 drirectory.
You can open it later on in Vivado 2014.3 and build the bitstream. |
wzab |
4038d 18h |
/fade_ether_protocol/trunk/stable_jumbo_frames_version/fpga/src/ |
