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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 57

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Rev Log message Author Age Path
57 - decimal floating-point IEEE format encode/decode robfinch 1421d 13h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1446d 13h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization
robfinch 1447d 05h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1447d 19h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1448d 23h /ft816float/trunk/rtl/verilog2/
51 - got rid of 'DF0' robfinch 1449d 02h /ft816float/trunk/rtl/verilog2/
50 - added decimal floating-point adder robfinch 1449d 10h /ft816float/trunk/rtl/verilog2/
49 - pipelining robfinch 1469d 15h /ft816float/trunk/rtl/verilog2/
48 - refactoring to use packages robfinch 1493d 23h /ft816float/trunk/rtl/verilog2/
35 - additional pipelining in divider
- radix4 primitive
robfinch 1709d 13h /ft816float/trunk/rtl/verilog2/
34 - add pipeline stage in divider robfinch 1709d 16h /ft816float/trunk/rtl/verilog2/
33 - mult114 for FMA robfinch 1962d 00h /ft816float/trunk/rtl/verilog2/
32 - FMA, test bench for FMA robfinch 1962d 00h /ft816float/trunk/rtl/verilog2/
31 - preserve nan sign in addsub robfinch 1962d 12h /ft816float/trunk/rtl/verilog2/
30 - move load signal to bottom robfinch 1978d 07h /ft816float/trunk/rtl/verilog2/
29 - refactor with FPWID and EXTRA_BITS
- Nan propagation
robfinch 1978d 15h /ft816float/trunk/rtl/verilog2/

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