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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 73

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Rev Log message Author Age Path
73 - fix Karatsuba carry chain bug robfinch 1006d 22h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 1007d 00h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 1014d 21h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 1015d 04h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 1019d 02h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 1019d 06h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 1019d 08h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 1019d 08h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 1019d 08h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 1019d 21h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 1019d 23h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 1020d 03h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1281d 08h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1422d 21h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1447d 21h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1448d 14h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1449d 03h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1450d 07h /ft816float/trunk/rtl/verilog2/
51 - got rid of 'DF0' robfinch 1450d 10h /ft816float/trunk/rtl/verilog2/
50 - added decimal floating-point adder robfinch 1450d 18h /ft816float/trunk/rtl/verilog2/

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