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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 74

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Rev Log message Author Age Path
74 - added single precision combo logic only version of FMA robfinch 885d 06h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 1056d 06h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 1056d 09h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 1064d 05h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 1064d 12h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 1068d 11h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 1068d 14h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 1068d 16h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 1068d 17h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 1068d 17h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 1069d 06h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 1069d 07h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 1069d 12h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1330d 16h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1472d 05h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1497d 06h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1497d 22h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1498d 11h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1499d 16h /ft816float/trunk/rtl/verilog2/
51 - got rid of 'DF0' robfinch 1499d 19h /ft816float/trunk/rtl/verilog2/
50 - added decimal floating-point adder robfinch 1500d 03h /ft816float/trunk/rtl/verilog2/
49 - pipelining robfinch 1520d 07h /ft816float/trunk/rtl/verilog2/
48 - refactoring to use packages robfinch 1544d 15h /ft816float/trunk/rtl/verilog2/
35 - additional pipelining in divider
- radix4 primitive		 robfinch 1760d 06h /ft816float/trunk/rtl/verilog2/
34 - add pipeline stage in divider robfinch 1760d 09h /ft816float/trunk/rtl/verilog2/
33 - mult114 for FMA robfinch 2012d 17h /ft816float/trunk/rtl/verilog2/
32 - FMA, test bench for FMA robfinch 2012d 17h /ft816float/trunk/rtl/verilog2/
31 - preserve nan sign in addsub robfinch 2013d 05h /ft816float/trunk/rtl/verilog2/
30 - move load signal to bottom robfinch 2029d 00h /ft816float/trunk/rtl/verilog2/
29 - refactor with FPWID and EXTRA_BITS
- Nan propagation		 robfinch 2029d 08h /ft816float/trunk/rtl/verilog2/

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