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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 75

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Rev Log message Author Age Path
75 - add triple precision decimal float robfinch 1132d 20h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 1240d 13h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 1411d 13h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 1411d 16h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 1419d 12h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 1419d 19h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 1423d 18h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 1423d 22h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 1424d 00h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 1424d 00h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 1424d 00h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 1424d 13h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 1424d 15h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 1424d 19h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1686d 00h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1827d 13h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1852d 13h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1853d 05h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1853d 19h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1854d 23h /ft816float/trunk/rtl/verilog2/

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