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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 75

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Rev Log message Author Age Path
75 - add triple precision decimal float robfinch 670d 03h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 777d 21h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 948d 21h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 948d 23h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 956d 20h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 957d 03h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 961d 01h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 961d 05h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 961d 07h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 961d 07h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 961d 07h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 961d 20h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 961d 22h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 962d 02h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1223d 07h /ft816float/trunk/rtl/verilog2/
57 - decimal floating-point IEEE format encode/decode robfinch 1364d 20h /ft816float/trunk/rtl/verilog2/
56 - decimal square root function robfinch 1389d 20h /ft816float/trunk/rtl/verilog2/
55 - add storage format
- parameterization		 robfinch 1390d 13h /ft816float/trunk/rtl/verilog2/
54 - add decimal float divider robfinch 1391d 02h /ft816float/trunk/rtl/verilog2/
53 - added decimal floating-point multiplier robfinch 1392d 07h /ft816float/trunk/rtl/verilog2/

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