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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 81

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Rev Log message Author Age Path
81 - timing delay on divide
- change adder in multiply		 robfinch 764d 14h /ft816float/trunk/rtl/verilog2/
80 - improve decimal float divide robfinch 764d 20h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 766d 04h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function		 robfinch 766d 15h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 768d 15h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 768d 21h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 876d 14h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 1047d 14h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 1047d 17h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 1055d 13h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 1055d 20h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 1059d 19h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 1059d 23h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 1060d 01h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 1060d 01h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias		 robfinch 1060d 01h /ft816float/trunk/rtl/verilog2/
62 - fix overflow status
- license comment		 robfinch 1060d 14h /ft816float/trunk/rtl/verilog2/
60 - decimal float <-> int converters robfinch 1060d 16h /ft816float/trunk/rtl/verilog2/
59 - bin to bcd and bcd to bin converters robfinch 1060d 20h /ft816float/trunk/rtl/verilog2/
58 - generic redor robfinch 1322d 01h /ft816float/trunk/rtl/verilog2/

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