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URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 85

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Rev Log message Author Age Path
85 - improve divider *10 robfinch 767d 04h /ft816float/trunk/rtl/verilog2/
84 - improve DPD divider robfinch 767d 07h /ft816float/trunk/rtl/verilog2/
83 - sign of zero is positive robfinch 767d 09h /ft816float/trunk/rtl/verilog2/
82 - improved divider robfinch 767d 09h /ft816float/trunk/rtl/verilog2/
81 - timing delay on divide
- change adder in multiply
robfinch 767d 19h /ft816float/trunk/rtl/verilog2/
80 - improve decimal float divide robfinch 768d 01h /ft816float/trunk/rtl/verilog2/
79 - fix sticky infinity robfinch 769d 08h /ft816float/trunk/rtl/verilog2/
78 - BCD subtraction
- scaleb function
robfinch 769d 20h /ft816float/trunk/rtl/verilog2/
76 - adjust 9 to 7 robfinch 771d 20h /ft816float/trunk/rtl/verilog2/
75 - add triple precision decimal float robfinch 772d 01h /ft816float/trunk/rtl/verilog2/
74 - added single precision combo logic only version of FMA robfinch 879d 19h /ft816float/trunk/rtl/verilog2/
73 - fix Karatsuba carry chain bug robfinch 1050d 19h /ft816float/trunk/rtl/verilog2/
72 - fix: mult32x32 prod high order bits robfinch 1050d 22h /ft816float/trunk/rtl/verilog2/
71 - added decimal float reciprocal estimate robfinch 1058d 18h /ft816float/trunk/rtl/verilog2/
70 - fix carry out for BCD add / sub robfinch 1059d 01h /ft816float/trunk/rtl/verilog2/
68 - added decimal float compare robfinch 1063d 00h /ft816float/trunk/rtl/verilog2/
67 - adding decimal float divide robfinch 1063d 03h /ft816float/trunk/rtl/verilog2/
66 - BCD arith additions robfinch 1063d 05h /ft816float/trunk/rtl/verilog2/
65 -update dfdiv / dfmul robfinch 1063d 06h /ft816float/trunk/rtl/verilog2/
64 - add multiply 128
- fix exponent bias
robfinch 1063d 06h /ft816float/trunk/rtl/verilog2/

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