URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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Rev	Log message	Author	Age	Path
90	- sin / cosine	robfinch	559d 15h	/ft816float/trunk/rtl/verilog2/
89	- fix compare in DFPTrunc96	robfinch	715d 03h	/ft816float/trunk/rtl/verilog2/
88	- DPFTrunc() function	robfinch	715d 06h	/ft816float/trunk/rtl/verilog2/
86	- improve divider *10	robfinch	730d 09h	/ft816float/trunk/rtl/verilog2/
85	- improve divider *10	robfinch	730d 09h	/ft816float/trunk/rtl/verilog2/
84	- improve DPD divider	robfinch	730d 12h	/ft816float/trunk/rtl/verilog2/
83	- sign of zero is positive	robfinch	730d 14h	/ft816float/trunk/rtl/verilog2/
82	- improved divider	robfinch	730d 14h	/ft816float/trunk/rtl/verilog2/
81	- timing delay on divide - change adder in multiply	robfinch	731d 00h	/ft816float/trunk/rtl/verilog2/
80	- improve decimal float divide	robfinch	731d 06h	/ft816float/trunk/rtl/verilog2/
79	- fix sticky infinity	robfinch	732d 13h	/ft816float/trunk/rtl/verilog2/
78	- BCD subtraction - scaleb function	robfinch	733d 01h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	735d 01h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	735d 06h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	843d 00h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	1014d 00h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	1014d 03h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	1021d 23h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	1022d 06h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	1026d 04h	/ft816float/trunk/rtl/verilog2/

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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