URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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Rev	Log message	Author	Age	Path
90	- sin / cosine	robfinch	552d 06h	/ft816float/trunk/rtl/verilog2/
89	- fix compare in DFPTrunc96	robfinch	707d 18h	/ft816float/trunk/rtl/verilog2/
88	- DPFTrunc() function	robfinch	707d 22h	/ft816float/trunk/rtl/verilog2/
86	- improve divider *10	robfinch	723d 00h	/ft816float/trunk/rtl/verilog2/
85	- improve divider *10	robfinch	723d 00h	/ft816float/trunk/rtl/verilog2/
84	- improve DPD divider	robfinch	723d 03h	/ft816float/trunk/rtl/verilog2/
83	- sign of zero is positive	robfinch	723d 05h	/ft816float/trunk/rtl/verilog2/
82	- improved divider	robfinch	723d 06h	/ft816float/trunk/rtl/verilog2/
81	- timing delay on divide - change adder in multiply	robfinch	723d 15h	/ft816float/trunk/rtl/verilog2/
80	- improve decimal float divide	robfinch	723d 21h	/ft816float/trunk/rtl/verilog2/
79	- fix sticky infinity	robfinch	725d 05h	/ft816float/trunk/rtl/verilog2/
78	- BCD subtraction - scaleb function	robfinch	725d 17h	/ft816float/trunk/rtl/verilog2/
76	- adjust 9 to 7	robfinch	727d 16h	/ft816float/trunk/rtl/verilog2/
75	- add triple precision decimal float	robfinch	727d 22h	/ft816float/trunk/rtl/verilog2/
74	- added single precision combo logic only version of FMA	robfinch	835d 15h	/ft816float/trunk/rtl/verilog2/
73	- fix Karatsuba carry chain bug	robfinch	1006d 15h	/ft816float/trunk/rtl/verilog2/
72	- fix: mult32x32 prod high order bits	robfinch	1006d 18h	/ft816float/trunk/rtl/verilog2/
71	- added decimal float reciprocal estimate	robfinch	1014d 14h	/ft816float/trunk/rtl/verilog2/
70	- fix carry out for BCD add / sub	robfinch	1014d 21h	/ft816float/trunk/rtl/verilog2/
68	- added decimal float compare	robfinch	1018d 20h	/ft816float/trunk/rtl/verilog2/
67	- adding decimal float divide	robfinch	1019d 00h	/ft816float/trunk/rtl/verilog2/
66	- BCD arith additions	robfinch	1019d 02h	/ft816float/trunk/rtl/verilog2/
65	-update dfdiv / dfmul	robfinch	1019d 02h	/ft816float/trunk/rtl/verilog2/
64	- add multiply 128 - fix exponent bias	robfinch	1019d 02h	/ft816float/trunk/rtl/verilog2/
62	- fix overflow status - license comment	robfinch	1019d 15h	/ft816float/trunk/rtl/verilog2/
60	- decimal float <-> int converters	robfinch	1019d 17h	/ft816float/trunk/rtl/verilog2/
59	- bin to bcd and bcd to bin converters	robfinch	1019d 21h	/ft816float/trunk/rtl/verilog2/
58	- generic redor	robfinch	1281d 02h	/ft816float/trunk/rtl/verilog2/
57	- decimal floating-point IEEE format encode/decode	robfinch	1422d 15h	/ft816float/trunk/rtl/verilog2/
56	- decimal square root function	robfinch	1447d 15h	/ft816float/trunk/rtl/verilog2/

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Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] - Rev 90

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