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[/] [gpio/] [trunk/] [rtl/] [verilog/] - Rev 66

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Rev Log message Author Age Path
65 New directory structure. root 4486d 13h /gpio/trunk/rtl/verilog/
62 Reorganize core, add synchronization flops. simont 6184d 02h /gpio/trunk/rtl/verilog/
60 Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec andreje 6256d 02h /gpio/trunk/rtl/verilog/
56 added ECLK and NEC registers, all tests passed. gorand 6395d 22h /gpio/trunk/rtl/verilog/
52 ifndef directive is not supported by all tools. simons 6411d 18h /gpio/trunk/rtl/verilog/
36 bug fixed. all tests passed. gorand 6432d 11h /gpio/trunk/rtl/verilog/
34 added support for 8-bit access to registers. gorand 6436d 21h /gpio/trunk/rtl/verilog/
31 Bug fix. Interrupts were also asserted when condition was not met. lampret 6789d 12h /gpio/trunk/rtl/verilog/
29 Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. lampret 6796d 13h /gpio/trunk/rtl/verilog/
27 negedge flops are enabled by default. lampret 6985d 16h /gpio/trunk/rtl/verilog/
26 Removed zero padding as per Avi Shamli suggestion. lampret 7039d 14h /gpio/trunk/rtl/verilog/
25 Ports changed per Ran Aviram suggestions. lampret 7039d 14h /gpio/trunk/rtl/verilog/
24 Interrupt is asserted only when an input changes (code patch by Jacob Gorban) lampret 7044d 07h /gpio/trunk/rtl/verilog/
23 Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. lampret 7097d 16h /gpio/trunk/rtl/verilog/
22 Fixed two typos. lampret 7117d 17h /gpio/trunk/rtl/verilog/
21 Added RGPIO_INTS. lampret 7117d 18h /gpio/trunk/rtl/verilog/
20 Fixing style. lampret 7130d 14h /gpio/trunk/rtl/verilog/
19 Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) lampret 7131d 04h /gpio/trunk/rtl/verilog/
17 Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. lampret 7158d 08h /gpio/trunk/rtl/verilog/
15 Fixed wb_err_o. lampret 7173d 08h /gpio/trunk/rtl/verilog/

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