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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7020d 07h /
23 *** empty log message *** rherveille 7147d 13h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7157d 18h /
21 no message rherveille 7243d 19h /
20 Added Appendix A rherveille 7243d 19h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7247d 15h /
18 no message rherveille 7274d 11h /
17 C-include file.
Initial release
rherveille 7362d 15h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7374d 15h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7379d 13h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7379d 14h /
13 Fixed some synthesis warnings. rherveille 7390d 18h /
12 no message rherveille 7396d 09h /
11 Changed RST_LVL define to parameter. rherveille 7399d 17h /
10 Created new directory structure.
Added Verilog version.
rherveille 7421d 13h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 7491d 08h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 7491d 08h /
7 added some remarks, fixed some sensitivity lists rherveille 7560d 11h /
6 fixed typo txt -> txr rherveille 7564d 15h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 7571d 13h /

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