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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7587d 07h /
30 Small code simplifications rherveille 7587d 07h /
29 Core is now a Multimaster I2C controller rherveille 7587d 08h /
28 *** empty log message *** rherveille 7613d 01h /
27 Cleaned up code rherveille 7613d 01h /
26 *** empty log message *** rherveille 7616d 09h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7644d 05h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7644d 05h /
23 *** empty log message *** rherveille 7771d 11h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7781d 16h /
21 no message rherveille 7867d 16h /
20 Added Appendix A rherveille 7867d 16h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7871d 13h /
18 no message rherveille 7898d 09h /
17 C-include file.
Initial release
rherveille 7986d 13h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7998d 12h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8003d 11h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8003d 11h /
13 Fixed some synthesis warnings. rherveille 8014d 15h /
12 no message rherveille 8020d 07h /

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