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Rev Log message Author Age Path
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7722d 20h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7726d 18h /
33 Fixed a bug in the Command Register declaration. rherveille 7749d 03h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7759d 03h /
31 Core is now a Multimaster I2C controller. rherveille 7763d 04h /
30 Small code simplifications rherveille 7763d 04h /
29 Core is now a Multimaster I2C controller rherveille 7763d 05h /
28 *** empty log message *** rherveille 7788d 21h /
27 Cleaned up code rherveille 7788d 21h /
26 *** empty log message *** rherveille 7792d 05h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7820d 02h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7820d 02h /
23 *** empty log message *** rherveille 7947d 07h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7957d 12h /
21 no message rherveille 8043d 13h /
20 Added Appendix A rherveille 8043d 13h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 8047d 09h /
18 no message rherveille 8074d 05h /
17 C-include file.
Initial release
rherveille 8162d 10h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8174d 09h /

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