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Rev Log message Author Age Path
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8348d 05h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8353d 04h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8353d 04h /
13 Fixed some synthesis warnings. rherveille 8364d 08h /
12 no message rherveille 8369d 23h /
11 Changed RST_LVL define to parameter. rherveille 8373d 07h /
10 Created new directory structure.
Added Verilog version.
rherveille 8395d 03h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8464d 22h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8464d 22h /
7 added some remarks, fixed some sensitivity lists rherveille 8534d 01h /

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