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Rev Log message Author Age Path
49 Added testbench rherveille 7158d 08h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7159d 16h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7168d 12h /
46 Fixed slave address MSB='1' bug rherveille 7243d 13h /
45 Added slave address configurability rherveille 7243d 13h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7328d 16h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7328d 16h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7338d 13h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7338d 13h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7338d 13h /
39 Forgot an 'end if' :-/ rherveille 7358d 09h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7361d 17h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7398d 09h /
36 Fixed cmd_ack generation item (no bug). rherveille 7513d 10h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7547d 00h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7550d 22h /
33 Fixed a bug in the Command Register declaration. rherveille 7573d 07h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7583d 07h /
31 Core is now a Multimaster I2C controller. rherveille 7587d 08h /
30 Small code simplifications rherveille 7587d 08h /

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