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Rev Log message Author Age Path
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6860d 21h /
54 Fixed scl, sda delay. rherveille 6860d 21h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7156d 18h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7156d 19h /
51 Fixed simulation issue when writing to CR register rherveille 7210d 20h /
50 *** empty log message *** rherveille 7225d 15h /
49 Added testbench rherveille 7225d 15h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7226d 23h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7235d 19h /
46 Fixed slave address MSB='1' bug rherveille 7310d 19h /
45 Added slave address configurability rherveille 7310d 19h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7395d 22h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7395d 22h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7405d 20h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7405d 20h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7405d 20h /
39 Forgot an 'end if' :-/ rherveille 7425d 16h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7428d 23h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7465d 15h /
36 Fixed cmd_ack generation item (no bug). rherveille 7580d 16h /

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