Subversion Repositories i2c

[/] - Rev 57


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6114d 00h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6666d 22h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6668d 00h /
54 Fixed scl, sda delay. rherveille 6668d 00h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6963d 22h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6963d 22h /
51 Fixed simulation issue when writing to CR register rherveille 7017d 23h /
50 *** empty log message *** rherveille 7032d 18h /
49 Added testbench rherveille 7032d 18h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7034d 02h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7042d 22h /
46 Fixed slave address MSB='1' bug rherveille 7117d 22h /
45 Added slave address configurability rherveille 7117d 22h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7203d 01h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7203d 01h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7212d 23h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7212d 23h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7212d 23h /
39 Forgot an 'end if' :-/ rherveille 7232d 19h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7236d 02h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.