URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 61

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
61	Removed synopsys link; it's not used	rherveille	6229d 01h	/
60	Added missing semicolons ';' on endif	rherveille	6405d 22h	/
59	fixed short scl high pulse after clock stretch	rherveille	6410d 23h	/
58	fixed (n)ack generation	rherveille	6443d 01h	/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6443d 01h	/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6995d 22h	/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	6997d 00h	/
54	Fixed scl, sda delay.	rherveille	6997d 00h	/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7292d 22h	/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7292d 23h	/
51	Fixed simulation issue when writing to CR register	rherveille	7347d 00h	/
50	* empty log message *	rherveille	7361d 18h	/
49	Added testbench	rherveille	7361d 18h	/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7363d 02h	/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7371d 22h	/
46	Fixed slave address MSB='1' bug	rherveille	7446d 23h	/
45	Added slave address configurability	rherveille	7446d 23h	/
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7532d 01h	/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7532d 01h	/
42	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7541d 23h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories i2c

[/] - Rev 61

Filtering Options