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Rev Log message Author Age Path
46 Fixed slave address MSB='1' bug rherveille 7440d 07h /
45 Added slave address configurability rherveille 7440d 07h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7525d 10h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7525d 10h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7535d 08h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7535d 08h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7535d 08h /
39 Forgot an 'end if' :-/ rherveille 7555d 03h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7558d 11h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7595d 03h /

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