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Rev Log message Author Age Path
50 *** empty log message *** rherveille 7333d 22h /
49 Added testbench rherveille 7333d 23h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7335d 06h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7344d 02h /
46 Fixed slave address MSB='1' bug rherveille 7419d 03h /
45 Added slave address configurability rherveille 7419d 03h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7504d 06h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7504d 06h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7514d 04h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7514d 04h /

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