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Rev Log message Author Age Path
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4517d 15h /
71 Fixed double wishbone write in a single access rherveille 4517d 15h /
70 Added old uploaded documents to new repository. root 4825d 18h /
69 Added old uploaded documents to new repository. root 4826d 09h /
68 New directory structure. root 4826d 09h /
67 Fixed slave_wait clocked event syntax rherveille 4859d 11h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4874d 10h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4874d 20h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4874d 21h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4874d 21h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4875d 11h /
61 Removed synopsys link; it's not used rherveille 5529d 22h /
60 Added missing semicolons ';' on endif rherveille 5706d 19h /
59 fixed short scl high pulse after clock stretch rherveille 5711d 20h /
58 fixed (n)ack generation rherveille 5743d 22h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5743d 22h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6296d 20h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6297d 22h /
54 Fixed scl, sda delay. rherveille 6297d 22h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6593d 19h /

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