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Subversion Repositories i2c

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Rev	Log message	Author	Age	Path
72	Fixed AL generation Added median filter on SDA and SCL inputs	rherveille	5214d 23h	/
71	Fixed double wishbone write in a single access	rherveille	5214d 23h	/
70	Added old uploaded documents to new repository.	root	5523d 02h	/
69	Added old uploaded documents to new repository.	root	5523d 17h	/
68	New directory structure.	root	5523d 17h	/
67	Fixed slave_wait clocked event syntax	rherveille	5556d 19h	/
66	Fixed type iscl_oen instead of scl_oen	rherveille	5571d 18h	/
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5572d 04h	/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5572d 05h	/
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5572d 05h	/
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5572d 19h	/
61	Removed synopsys link; it's not used	rherveille	6227d 06h	/
60	Added missing semicolons ';' on endif	rherveille	6404d 03h	/
59	fixed short scl high pulse after clock stretch	rherveille	6409d 04h	/
58	fixed (n)ack generation	rherveille	6441d 06h	/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6441d 06h	/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6994d 04h	/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	6995d 06h	/
54	Fixed scl, sda delay.	rherveille	6995d 06h	/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7291d 03h	/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7291d 04h	/
51	Fixed simulation issue when writing to CR register	rherveille	7345d 05h	/
50	* empty log message *	rherveille	7359d 23h	/
49	Added testbench	rherveille	7360d 00h	/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7361d 07h	/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7370d 03h	/
46	Fixed slave address MSB='1' bug	rherveille	7445d 04h	/
45	Added slave address configurability	rherveille	7445d 04h	/
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7530d 07h	/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7530d 07h	/

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[/] - Rev 72

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