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Rev Log message Author Age Path
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6970d 02h /
54 Fixed scl, sda delay. rherveille 6970d 02h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7265d 23h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7266d 00h /
51 Fixed simulation issue when writing to CR register rherveille 7320d 01h /
50 *** empty log message *** rherveille 7334d 20h /
49 Added testbench rherveille 7334d 20h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7336d 04h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7345d 00h /
46 Fixed slave address MSB='1' bug rherveille 7420d 00h /

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