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Subversion Repositories i2c

[/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 4247d 16h /
75 Fixed sSDA generation rherveille 4253d 12h /
74 Added SCL/SDA line filter rherveille 4392d 09h /
73 Fixed double wishbone write in a single access rherveille 4392d 09h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4392d 09h /
71 Fixed double wishbone write in a single access rherveille 4392d 09h /
70 Added old uploaded documents to new repository. root 4700d 12h /
69 Added old uploaded documents to new repository. root 4701d 03h /
68 New directory structure. root 4701d 03h /
67 Fixed slave_wait clocked event syntax rherveille 4734d 05h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4749d 05h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4749d 15h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4749d 15h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4749d 15h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4750d 05h /
61 Removed synopsys link; it's not used rherveille 5404d 16h /
60 Added missing semicolons ';' on endif rherveille 5581d 13h /
59 fixed short scl high pulse after clock stretch rherveille 5586d 15h /
58 fixed (n)ack generation rherveille 5618d 16h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5618d 16h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6171d 14h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6172d 16h /
54 Fixed scl, sda delay. rherveille 6172d 16h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6468d 13h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6468d 14h /
51 Fixed simulation issue when writing to CR register rherveille 6522d 15h /
50 *** empty log message *** rherveille 6537d 10h /
49 Added testbench rherveille 6537d 10h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6538d 17h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6547d 14h /

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