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[/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5239d 05h /
75 Fixed sSDA generation rherveille 5245d 02h /
74 Added SCL/SDA line filter rherveille 5383d 22h /
73 Fixed double wishbone write in a single access rherveille 5383d 22h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5383d 23h /
71 Fixed double wishbone write in a single access rherveille 5383d 23h /
70 Added old uploaded documents to new repository. root 5692d 01h /
69 Added old uploaded documents to new repository. root 5692d 17h /
68 New directory structure. root 5692d 17h /
67 Fixed slave_wait clocked event syntax rherveille 5725d 19h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5740d 18h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5741d 04h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5741d 04h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5741d 05h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5741d 19h /
61 Removed synopsys link; it's not used rherveille 6396d 06h /
60 Added missing semicolons ';' on endif rherveille 6573d 03h /
59 fixed short scl high pulse after clock stretch rherveille 6578d 04h /
58 fixed (n)ack generation rherveille 6610d 06h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6610d 06h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7163d 03h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7164d 06h /
54 Fixed scl, sda delay. rherveille 7164d 06h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7460d 03h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7460d 04h /
51 Fixed simulation issue when writing to CR register rherveille 7514d 05h /
50 *** empty log message *** rherveille 7528d 23h /
49 Added testbench rherveille 7528d 23h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7530d 07h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7539d 03h /

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