OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 76

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 7163d 04h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7164d 06h /
54 Fixed scl, sda delay. rherveille 7164d 06h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7460d 04h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7460d 05h /
51 Fixed simulation issue when writing to CR register rherveille 7514d 05h /
50 *** empty log message *** rherveille 7529d 00h /
49 Added testbench rherveille 7529d 00h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7530d 08h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7539d 04h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.