URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] - Rev 70

Rev	Log message	Author	Age	Path
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7985d 02h	/i2c/tags/asyst_2/
21	no message	rherveille	8071d 03h	/i2c/tags/asyst_2/
20	Added Appendix A	rherveille	8071d 03h	/i2c/tags/asyst_2/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8074d 23h	/i2c/tags/asyst_2/
18	no message	rherveille	8101d 19h	/i2c/tags/asyst_2/
17	C-include file. Initial release	rherveille	8190d 00h	/i2c/tags/asyst_2/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8201d 23h	/i2c/tags/asyst_2/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8206d 22h	/i2c/tags/asyst_2/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8206d 22h	/i2c/tags/asyst_2/
13	Fixed some synthesis warnings.	rherveille	8218d 02h	/i2c/tags/asyst_2/