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[/] [i2c/] [tags/] [rel_1/] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 5517d 00h /i2c/tags/rel_1/
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7523d 14h /tags/rel_1/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7523d 14h /trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7533d 12h /trunk/
39 Forgot an 'end if' :-/ rherveille 7553d 08h /trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7556d 16h /trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7593d 07h /trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7708d 08h /trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7741d 23h /trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7745d 21h /trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7768d 06h /trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7778d 06h /trunk/
31 Core is now a Multimaster I2C controller. rherveille 7782d 07h /trunk/
30 Small code simplifications rherveille 7782d 07h /trunk/
29 Core is now a Multimaster I2C controller rherveille 7782d 08h /trunk/
28 *** empty log message *** rherveille 7808d 00h /trunk/
27 Cleaned up code rherveille 7808d 00h /trunk/
26 *** empty log message *** rherveille 7811d 08h /trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7839d 05h /trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7839d 05h /trunk/

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