URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] - Rev 14

Rev	Log message	Author	Age	Path
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8198d 11h	/i2c/tags/rel_1/
13	Fixed some synthesis warnings.	rherveille	8209d 15h	/i2c/tags/rel_1/
12	no message	rherveille	8215d 06h	/i2c/tags/rel_1/
11	Changed RST_LVL define to parameter.	rherveille	8218d 14h	/i2c/tags/rel_1/
10	Created new directory structure. Added Verilog version.	rherveille	8240d 10h	/i2c/tags/rel_1/
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8310d 05h	/i2c/tags/rel_1/
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8310d 05h	/i2c/tags/rel_1/
7	added some remarks, fixed some sensitivity lists	rherveille	8379d 08h	/i2c/tags/rel_1/
6	fixed typo txt -> txr	rherveille	8383d 12h	/i2c/tags/rel_1/
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8390d 10h	/i2c/tags/rel_1/
4	WISHBONE I2C Master Core: initial release	rherveille	8442d 13h	/i2c/tags/rel_1/
2	initial release	rherveille	8504d 13h	/i2c/tags/rel_1/
1	Standard project directories initialized by cvs2svn.		8504d 13h	/i2c/tags/rel_1/