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[/] [i2c/] [tags/] [rel_1/] - Rev 69


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Rev Log message Author Age Path
68 New directory structure. root 5123d 16h /i2c/tags/rel_1/
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7130d 06h /tags/rel_1/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7130d 06h /trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7140d 04h /trunk/
39 Forgot an 'end if' :-/ rherveille 7160d 00h /trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7163d 07h /trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7199d 23h /trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7315d 00h /trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7348d 14h /trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7352d 12h /trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7374d 22h /trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7384d 21h /trunk/
31 Core is now a Multimaster I2C controller. rherveille 7388d 22h /trunk/
30 Small code simplifications rherveille 7388d 22h /trunk/
29 Core is now a Multimaster I2C controller rherveille 7388d 23h /trunk/
28 *** empty log message *** rherveille 7414d 16h /trunk/
27 Cleaned up code rherveille 7414d 16h /trunk/
26 *** empty log message *** rherveille 7418d 00h /trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7445d 20h /trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7445d 20h /trunk/
23 *** empty log message *** rherveille 7573d 02h /trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7583d 07h /trunk/
21 no message rherveille 7669d 08h /trunk/
20 Added Appendix A rherveille 7669d 08h /trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7673d 04h /trunk/
18 no message rherveille 7700d 00h /trunk/
17 C-include file.
Initial release
rherveille 7788d 04h /trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7800d 04h /trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7805d 02h /trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7805d 03h /trunk/

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