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Rev Log message Author Age Path
31 Core is now a Multimaster I2C controller. rherveille 7575d 21h /i2c/trunk/
30 Small code simplifications rherveille 7575d 21h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7575d 22h /i2c/trunk/
28 *** empty log message *** rherveille 7601d 14h /i2c/trunk/
27 Cleaned up code rherveille 7601d 14h /i2c/trunk/
26 *** empty log message *** rherveille 7604d 22h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7632d 19h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7632d 19h /i2c/trunk/
23 *** empty log message *** rherveille 7760d 00h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7770d 05h /i2c/trunk/
21 no message rherveille 7856d 06h /i2c/trunk/
20 Added Appendix A rherveille 7856d 06h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7860d 02h /i2c/trunk/
18 no message rherveille 7886d 22h /i2c/trunk/
17 C-include file.
Initial release
rherveille 7975d 03h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7987d 02h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7992d 01h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7992d 01h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8003d 05h /i2c/trunk/
12 no message rherveille 8008d 20h /i2c/trunk/

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