URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 35

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7749d 02h	/i2c/trunk/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7753d 00h	/i2c/trunk/
33	Fixed a bug in the Command Register declaration.	rherveille	7775d 09h	/i2c/trunk/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7785d 09h	/i2c/trunk/
31	Core is now a Multimaster I2C controller.	rherveille	7789d 10h	/i2c/trunk/
30	Small code simplifications	rherveille	7789d 10h	/i2c/trunk/
29	Core is now a Multimaster I2C controller	rherveille	7789d 11h	/i2c/trunk/
28	* empty log message *	rherveille	7815d 04h	/i2c/trunk/
27	Cleaned up code	rherveille	7815d 04h	/i2c/trunk/
26	* empty log message *	rherveille	7818d 12h	/i2c/trunk/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7846d 08h	/i2c/trunk/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7846d 08h	/i2c/trunk/
23	* empty log message *	rherveille	7973d 13h	/i2c/trunk/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7983d 19h	/i2c/trunk/
21	no message	rherveille	8069d 19h	/i2c/trunk/
20	Added Appendix A	rherveille	8069d 19h	/i2c/trunk/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8073d 16h	/i2c/trunk/
18	no message	rherveille	8100d 12h	/i2c/trunk/
17	C-include file. Initial release	rherveille	8188d 16h	/i2c/trunk/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8200d 15h	/i2c/trunk/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 35

Filtering Options