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[/] [i2c/] [trunk/] - Rev 38

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Rev Log message Author Age Path
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7558d 16h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7595d 08h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7710d 09h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7743d 23h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7747d 21h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7770d 07h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7780d 06h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7784d 07h /i2c/trunk/
30 Small code simplifications rherveille 7784d 07h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7784d 08h /i2c/trunk/
28 *** empty log message *** rherveille 7810d 01h /i2c/trunk/
27 Cleaned up code rherveille 7810d 01h /i2c/trunk/
26 *** empty log message *** rherveille 7813d 09h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7841d 05h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7841d 05h /i2c/trunk/
23 *** empty log message *** rherveille 7968d 11h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7978d 16h /i2c/trunk/
21 no message rherveille 8064d 16h /i2c/trunk/
20 Added Appendix A rherveille 8064d 17h /i2c/trunk/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8068d 13h /i2c/trunk/
18 no message rherveille 8095d 09h /i2c/trunk/
17 C-include file.
Initial release		 rherveille 8183d 13h /i2c/trunk/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8195d 13h /i2c/trunk/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8200d 11h /i2c/trunk/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8200d 11h /i2c/trunk/
13 Fixed some synthesis warnings. rherveille 8211d 16h /i2c/trunk/
12 no message rherveille 8217d 07h /i2c/trunk/
11 Changed RST_LVL define to parameter. rherveille 8220d 15h /i2c/trunk/
10 Created new directory structure.
Added Verilog version.		 rherveille 8242d 11h /i2c/trunk/
9 Created directory structure (documentation, vhdl, verilog) rherveille 8312d 06h /i2c/trunk/

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