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[/] [i2c/] [trunk/] - Rev 40

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Rev Log message Author Age Path
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7535d 22h /i2c/trunk/
39 Forgot an 'end if' :-/ rherveille 7555d 17h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7559d 01h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7595d 17h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7710d 18h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7744d 08h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7748d 06h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 7770d 15h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7780d 15h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 7784d 16h /i2c/trunk/
30 Small code simplifications rherveille 7784d 16h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 7784d 17h /i2c/trunk/
28 *** empty log message *** rherveille 7810d 10h /i2c/trunk/
27 Cleaned up code rherveille 7810d 10h /i2c/trunk/
26 *** empty log message *** rherveille 7813d 18h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7841d 14h /i2c/trunk/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7841d 14h /i2c/trunk/
23 *** empty log message *** rherveille 7968d 19h /i2c/trunk/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7979d 00h /i2c/trunk/
21 no message rherveille 8065d 01h /i2c/trunk/

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