OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 47

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7967d 06h /i2c/trunk/
46 Fixed slave address MSB='1' bug rherveille 8042d 07h /i2c/trunk/
45 Added slave address configurability rherveille 8042d 07h /i2c/trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 8127d 09h /i2c/trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 8137d 07h /i2c/trunk/
39 Forgot an 'end if' :-/ rherveille 8157d 03h /i2c/trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 8160d 11h /i2c/trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 8197d 03h /i2c/trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 8312d 03h /i2c/trunk/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 8345d 18h /i2c/trunk/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 8349d 16h /i2c/trunk/
33 Fixed a bug in the Command Register declaration. rherveille 8372d 01h /i2c/trunk/
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 8382d 01h /i2c/trunk/
31 Core is now a Multimaster I2C controller. rherveille 8386d 02h /i2c/trunk/
30 Small code simplifications rherveille 8386d 02h /i2c/trunk/
29 Core is now a Multimaster I2C controller rherveille 8386d 03h /i2c/trunk/
28 *** empty log message *** rherveille 8411d 19h /i2c/trunk/
27 Cleaned up code rherveille 8411d 20h /i2c/trunk/
26 *** empty log message *** rherveille 8415d 03h /i2c/trunk/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 8443d 00h /i2c/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.