OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] - Rev 70

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 New directory structure. root 4952d 13h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 4985d 15h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 5000d 15h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5001d 01h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5001d 01h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5001d 01h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5001d 15h /trunk/
61 Removed synopsys link; it's not used rherveille 5656d 02h /trunk/
60 Added missing semicolons ';' on endif rherveille 5832d 23h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 5838d 01h /trunk/
58 fixed (n)ack generation rherveille 5870d 02h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5870d 02h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6423d 00h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6424d 02h /trunk/
54 Fixed scl, sda delay. rherveille 6424d 02h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6720d 00h /trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6720d 00h /trunk/
51 Fixed simulation issue when writing to CR register rherveille 6774d 01h /trunk/
50 *** empty log message *** rherveille 6788d 20h /trunk/
49 Added testbench rherveille 6788d 20h /trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6790d 04h /trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6799d 00h /trunk/
46 Fixed slave address MSB='1' bug rherveille 6874d 00h /trunk/
45 Added slave address configurability rherveille 6874d 00h /trunk/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 6959d 03h /trunk/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 6969d 01h /trunk/
39 Forgot an 'end if' :-/ rherveille 6988d 21h /trunk/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 6992d 04h /trunk/
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7028d 20h /trunk/
36 Fixed cmd_ack generation item (no bug). rherveille 7143d 21h /trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.