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Rev Log message Author Age Path
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4215d 09h /i2c/trunk/
71 Fixed double wishbone write in a single access rherveille 4215d 09h /i2c/trunk/
68 New directory structure. root 4524d 03h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 4557d 05h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 4572d 05h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4572d 15h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4572d 15h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4572d 15h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4573d 05h /trunk/
61 Removed synopsys link; it's not used rherveille 5227d 17h /trunk/
60 Added missing semicolons ';' on endif rherveille 5404d 13h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 5409d 15h /trunk/
58 fixed (n)ack generation rherveille 5441d 16h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5441d 16h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5994d 14h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 5995d 16h /trunk/
54 Fixed scl, sda delay. rherveille 5995d 16h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6291d 14h /trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6291d 15h /trunk/
51 Fixed simulation issue when writing to CR register rherveille 6345d 15h /trunk/

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