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[/] [i2c/] [trunk/] - Rev 76


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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 3721d 20h /i2c/trunk/
75 Fixed sSDA generation rherveille 3727d 16h /i2c/trunk/
74 Added SCL/SDA line filter rherveille 3866d 13h /i2c/trunk/
73 Fixed double wishbone write in a single access rherveille 3866d 13h /i2c/trunk/
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 3866d 13h /i2c/trunk/
71 Fixed double wishbone write in a single access rherveille 3866d 13h /i2c/trunk/
68 New directory structure. root 4175d 07h /i2c/trunk/
67 Fixed slave_wait clocked event syntax rherveille 4208d 09h /trunk/
66 Fixed type iscl_oen instead of scl_oen rherveille 4223d 09h /trunk/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4223d 19h /trunk/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4223d 19h /trunk/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4223d 19h /trunk/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4224d 09h /trunk/
61 Removed synopsys link; it's not used rherveille 4878d 20h /trunk/
60 Added missing semicolons ';' on endif rherveille 5055d 17h /trunk/
59 fixed short scl high pulse after clock stretch rherveille 5060d 19h /trunk/
58 fixed (n)ack generation rherveille 5092d 20h /trunk/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5092d 20h /trunk/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5645d 18h /trunk/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 5646d 20h /trunk/
54 Fixed scl, sda delay. rherveille 5646d 20h /trunk/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 5942d 18h /trunk/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 5942d 18h /trunk/
51 Fixed simulation issue when writing to CR register rherveille 5996d 19h /trunk/
50 *** empty log message *** rherveille 6011d 14h /trunk/
49 Added testbench rherveille 6011d 14h /trunk/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6012d 22h /trunk/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6021d 18h /trunk/
46 Fixed slave address MSB='1' bug rherveille 6096d 18h /trunk/
45 Added slave address configurability rherveille 6096d 18h /trunk/

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