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URL https://opencores.org/ocsvn/i2c/i2c/trunk

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[/] [i2c/] [trunk/] [bench/] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 4217d 01h /i2c/trunk/bench/
58 fixed (n)ack generation rherveille 5134d 15h /trunk/bench/
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5687d 12h /trunk/bench/
54 Fixed scl, sda delay. rherveille 5688d 14h /trunk/bench/
50 *** empty log message *** rherveille 6053d 08h /trunk/bench/
49 Added testbench rherveille 6053d 08h /trunk/bench/
46 Fixed slave address MSB='1' bug rherveille 6138d 13h /trunk/bench/
45 Added slave address configurability rherveille 6138d 13h /trunk/bench/
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 6223d 15h /trunk/bench/
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 6539d 06h /trunk/bench/
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 6766d 13h /trunk/bench/
10 Created new directory structure.
Added Verilog version.
rherveille 6940d 11h /trunk/bench/

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