URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] - Rev 72

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5524d 08h	/i2c/trunk/bench/
58	fixed (n)ack generation	rherveille	6441d 22h	/trunk/bench/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6994d 19h	/trunk/bench/
54	Fixed scl, sda delay.	rherveille	6995d 21h	/trunk/bench/
50	* empty log message *	rherveille	7360d 15h	/trunk/bench/
49	Added testbench	rherveille	7360d 15h	/trunk/bench/
46	Fixed slave address MSB='1' bug	rherveille	7445d 20h	/trunk/bench/
45	Added slave address configurability	rherveille	7445d 20h	/trunk/bench/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7530d 22h	/trunk/bench/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7846d 13h	/trunk/bench/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8073d 20h	/trunk/bench/
10	Created new directory structure. Added Verilog version.	rherveille	8247d 18h	/trunk/bench/