URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] - Rev 68

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5519d 23h	/i2c/trunk/bench/verilog/
58	fixed (n)ack generation	rherveille	6437d 13h	/i2c/trunk/bench/verilog/
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	6990d 10h	/i2c/trunk/bench/verilog/
54	Fixed scl, sda delay.	rherveille	6991d 12h	/i2c/trunk/bench/verilog/
50	* empty log message *	rherveille	7356d 06h	/i2c/trunk/bench/verilog/
49	Added testbench	rherveille	7356d 06h	/i2c/trunk/bench/verilog/
46	Fixed slave address MSB='1' bug	rherveille	7441d 11h	/i2c/trunk/bench/verilog/
45	Added slave address configurability	rherveille	7441d 11h	/i2c/trunk/bench/verilog/
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7526d 13h	/i2c/trunk/bench/verilog/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7842d 04h	/i2c/trunk/bench/verilog/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8069d 11h	/i2c/trunk/bench/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8243d 10h	/i2c/trunk/bench/verilog/