OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 52

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7286d 05h /i2c/trunk/rtl/
51 Fixed simulation issue when writing to CR register rherveille 7340d 06h /i2c/trunk/rtl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7356d 09h /i2c/trunk/rtl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7365d 05h /i2c/trunk/rtl/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7535d 06h /i2c/trunk/rtl/
39 Forgot an 'end if' :-/ rherveille 7555d 02h /i2c/trunk/rtl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7558d 10h /i2c/trunk/rtl/
36 Fixed cmd_ack generation item (no bug). rherveille 7710d 02h /i2c/trunk/rtl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7743d 16h /i2c/trunk/rtl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7747d 14h /i2c/trunk/rtl/
33 Fixed a bug in the Command Register declaration. rherveille 7770d 00h /i2c/trunk/rtl/
31 Core is now a Multimaster I2C controller. rherveille 7784d 00h /i2c/trunk/rtl/
30 Small code simplifications rherveille 7784d 00h /i2c/trunk/rtl/
29 Core is now a Multimaster I2C controller rherveille 7784d 01h /i2c/trunk/rtl/
28 *** empty log message *** rherveille 7809d 18h /i2c/trunk/rtl/
27 Cleaned up code rherveille 7809d 18h /i2c/trunk/rtl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7840d 22h /i2c/trunk/rtl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7978d 09h /i2c/trunk/rtl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8195d 06h /i2c/trunk/rtl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8200d 04h /i2c/trunk/rtl/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8200d 05h /i2c/trunk/rtl/
13 Fixed some synthesis warnings. rherveille 8211d 09h /i2c/trunk/rtl/
11 Changed RST_LVL define to parameter. rherveille 8220d 08h /i2c/trunk/rtl/
10 Created new directory structure.
Added Verilog version.		 rherveille 8242d 04h /i2c/trunk/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.