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[/] [i2c/] [trunk/] [rtl/] - Rev 64

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Rev Log message Author Age Path
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5574d 06h /i2c/trunk/rtl/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5574d 06h /i2c/trunk/rtl/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5574d 20h /i2c/trunk/rtl/
60 Added missing semicolons ';' on endif rherveille 6406d 04h /i2c/trunk/rtl/
59 fixed short scl high pulse after clock stretch rherveille 6411d 05h /i2c/trunk/rtl/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6443d 07h /i2c/trunk/rtl/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6997d 07h /i2c/trunk/rtl/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7293d 04h /i2c/trunk/rtl/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7293d 05h /i2c/trunk/rtl/
51 Fixed simulation issue when writing to CR register rherveille 7347d 06h /i2c/trunk/rtl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7363d 08h /i2c/trunk/rtl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7372d 04h /i2c/trunk/rtl/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7542d 06h /i2c/trunk/rtl/
39 Forgot an 'end if' :-/ rherveille 7562d 01h /i2c/trunk/rtl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7565d 09h /i2c/trunk/rtl/
36 Fixed cmd_ack generation item (no bug). rherveille 7717d 02h /i2c/trunk/rtl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7750d 16h /i2c/trunk/rtl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7754d 14h /i2c/trunk/rtl/
33 Fixed a bug in the Command Register declaration. rherveille 7776d 23h /i2c/trunk/rtl/
31 Core is now a Multimaster I2C controller. rherveille 7791d 00h /i2c/trunk/rtl/

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