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[/] [i2c/] [trunk/] [rtl/] - Rev 70

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Rev	Log message	Author	Age	Path
68	New directory structure.	root	5524d 03h	/i2c/trunk/rtl/
67	Fixed slave_wait clocked event syntax	rherveille	5557d 05h	/trunk/rtl/
66	Fixed type iscl_oen instead of scl_oen	rherveille	5572d 05h	/trunk/rtl/
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5572d 15h	/trunk/rtl/
64	Added SCL clock synchronization logic Fixed slave_wait signal generation	rherveille	5572d 15h	/trunk/rtl/
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5572d 15h	/trunk/rtl/
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5573d 05h	/trunk/rtl/
60	Added missing semicolons ';' on endif	rherveille	6404d 13h	/trunk/rtl/
59	fixed short scl high pulse after clock stretch	rherveille	6409d 15h	/trunk/rtl/
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6441d 16h	/trunk/rtl/
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	6995d 16h	/trunk/rtl/
53	Fixed previous fix :) Made a variable vs signal mistake.	rherveille	7291d 14h	/trunk/rtl/
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7291d 14h	/trunk/rtl/
51	Fixed simulation issue when writing to CR register	rherveille	7345d 15h	/trunk/rtl/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7361d 18h	/trunk/rtl/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7370d 14h	/trunk/rtl/
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7540d 15h	/trunk/rtl/
39	Forgot an 'end if' :-/	rherveille	7560d 11h	/trunk/rtl/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7563d 18h	/trunk/rtl/
36	Fixed cmd_ack generation item (no bug).	rherveille	7715d 11h	/trunk/rtl/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7749d 01h	/trunk/rtl/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7752d 23h	/trunk/rtl/
33	Fixed a bug in the Command Register declaration.	rherveille	7775d 09h	/trunk/rtl/
31	Core is now a Multimaster I2C controller.	rherveille	7789d 09h	/trunk/rtl/
30	Small code simplifications	rherveille	7789d 09h	/trunk/rtl/
29	Core is now a Multimaster I2C controller	rherveille	7789d 10h	/trunk/rtl/
28	* empty log message *	rherveille	7815d 03h	/trunk/rtl/
27	Cleaned up code	rherveille	7815d 03h	/trunk/rtl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7846d 07h	/trunk/rtl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7983d 18h	/trunk/rtl/

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[/] [i2c/] [trunk/] [rtl/] - Rev 70

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