OpenCores

URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Rev 76

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
74	Added SCL/SDA line filter	rherveille	5216d 11h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
68	New directory structure.	root	5525d 05h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5573d 17h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5574d 07h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6442d 19h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7292d 17h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7564d 21h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
36	Fixed cmd_ack generation item (no bug).	rherveille	7716d 13h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7750d 04h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
30	Small code simplifications	rherveille	7790d 12h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
29	Core is now a Multimaster I2C controller	rherveille	7790d 13h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
27	Cleaned up code	rherveille	7816d 05h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7847d 10h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7984d 20h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8206d 16h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
10	Created new directory structure. Added Verilog version.	rherveille	8248d 15h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.